Tag Archives: Gallium Arsenide

RF Transistors using more Germanium

So far, gallium arsenide was the choice of material for building fast radio frequency transistors. However, that scenario is changing fast. Germanium is fast catching up, as it is less expensive and more compatible with CMOS and silicon. In this connection, the European research institute Imec has presented a pair of papers featuring gate-all-around (GAA) transistors at the 2017 Symposia on VLSI Technology and Circuits in Japan. They claim that GAA transistors can outperform standard CMOS below the 10-nm node, while featuring source/drain contacts with resistances of the order of a billionth-of-an-ohm.

Imec claims their SiGe GAA FETs are super-fast, as they use scaled strained germanium p-channels. With diameters below the 10-nm range, the GAA FETs are integrated on a 300 mm platform, which gives them their superior electrostatic control. They achieve this by using high-pressure annealing (HPA)—the same technology used by Imec for their more traditional FinFET architecture.

According to Imec, they used pulsed-laser annealing and shallow gallium implantation techniques to achieve the very low source/drain resistivity. They claim to have achieved a new world record for resistances of one billionth of an ohm for the source/drain contacts of their p-MOS transistor.

That germanium-on-silicon transistors have the ability to outperform other technologies as radio frequency transceivers is already well known. In practice, this allows using the same CMOS technology throughout the transceiver and avoids using GaAs Pas, which has lattice structures incompatible to silicon.

However, beyond the 10 nm range of advanced nodes, there was no confirmation that SiGe could perform as well for FinFETs or for more advanced architectures such as the GAA FETs, least of all in the state-of-the-art wafers of 300 mm. According to Imec, using HPA, they were able to boost the performance and electrostatic control exceptionally for both p-channel FinFETs and GAAS.

Imec will be sharing their record-breaking billionth of an ohm per square centimeter for P-SiGe source/drain contacts with other CMOS members, namely, TSMC, Sony Semiconductor Solutions, SK Hynix, Samsung, Qualcom, Micron, Intel, Huawei, and GlobalFoundries.

Imec claims to have made it easier to go below the 10-nm range without sacrificing electrostatic control, by making architectural changes they have not yet disclosed. This allowed them to compensate for the smaller bandgap and larger permittivity of SiGe. According to Imec, this has also allowed them to make gate lengths of the order of 40 nm, and nanowires of about 9 nm, the shortest and the thinnest in the world. As a consequence, they claim to have lowered the sub-threshold slope of 79 mV/decade and the drain-induced barrier of 30 mV/V, while retaining the electrostatic control for their GAA-FETs.

By using HPA techniques, Imec is also claiming to have boosted the performance of both their germanium GAAs and FinFETs. Because of HPA at 450°C, Imec researchers were able to improve hole mobility and interface quality to 60 cm2/Vs. By optimizing the HPA technique, they could improve the electrostatic and overall performance of the GAA devices significantly. This allowed them to reach 60 nm lengths and achieve a Q-factor of 15. They were also able to lower the currents from 3 to 10-billionths of an amp per micron.