Electronic components, especially semiconductors have undergone a dramatic transformation over the past few decades. Starting from the through-hole packages, semiconductors evolved into the surface mount packaging, which is the default today. With the increase in packaging density, surface mount packaging is now limited to passive components mostly, while semiconductors are moving towards current technologies involving leadless packaging.
Modern technologies involve leadless packaging such as dual/quad flats with no leads (DFN/QFN), Ball Grid Arrays or BGAs and Chip Scale Packaging or CSP. Such innovative technologies are allowing the semiconductor industry to exploit the successive IC processing shrink and achieve product performances, which were thought impossible earlier
For example, consider a simple three-pin discrete device such as a MOSFET, typically used as a switching device that can conduct currents ranging from 0.1A to more than 100A at voltages surpassing 1000V. Applications as diverse as motor controls to battery management use MOSFETs.
Leadless packaging makes discrete devices more attractive because of the assembly efficiencies involved that makes them friendlier to the environment. Although several leadless solutions are possible for packaging MOSFETs – BGAs, CSPs and DFN/QFN – the governing factor here is mainly the market price pressure. Substrate costs may be expensive, making package material sets undesirable for BGA packaging. Moreover, capital expenditure required to changeover to full production with new packaging types such as BGAs and CSPs may increase the per-unit cost.
Consequently, BGA and CSP packaging is limited to discrete semiconductor applications where the average selling price is of a secondary consideration over more important parameters such as performance. At present, the traditional surface mount packages are being replaced by the more cost-effective alternatives leadless package solutions such as the DFN and QFN.
The manufacturing steps for a typical DFN package consists of six key processes. A silicon die is attached to a copper alloy or similar leadframe using a highly conductive epoxy resin. The package pads are then attached to the silicon die using wirebonds of aluminum or gold. The silicon and leadframe package is then hermetically sealed with a mold of a halogen-free compound. Sawing the molded lead frame yields the finished package product.
Leadless packages offer several advantages. They utilize the available board-space more efficiently, while improving the thermal performance of the device. For example, the SOT23 package, being one of the most widely used packages of the semiconductor industry, has a silicon-to-footprint ratio of 23%, while it occupies 8mm2 space on the printed circuit board. Comparatively, The DFN2020 package has a silicon-to-footprint ratio of 42%, which is nearly double that of the SOT23, while it occupies only 4mm2 space on the PCB. This leads to huge cost benefits to the manufacturing industry, while simultaneously increasing the electrical performance of the application.
The DFN package has a highly conductive copper alloy pad for the die, which is exposed to the outside of the package to be soldered. This larger area of contact between the DFN package and the printed circuit board results in a very low thermal impedance between the junction and the leads. This ensures not only a reliable contact, but also a higher thermal efficiency as compared to typical surface mount packages.