Switching power-conversion systems such as switching power supplies and power factor controllers increasingly demand higher energy efficiencies. For such energy-conscious designers, super-junction MOSFETs are a favored solution, as the technology allows smaller die sizes when considering key parameters such as on-resistance. This leads to an increase in current density while enabling designers to reduce circuit size. With increasing market adoption of this new technology goes up, other challenges are coming to the fore, mainly the requirement for improved noise performance.
High-end power supplies for equipment such as LED lighting, LCD TVs, notebook power adapters, medical power supplies, and tablet power supplies require reduced electromagnetic noise emission. Designers prefer using resonant switching topologies such as the LLC converter with zero-voltage switching, as these have inherently low electromagnetic emissions. Super-junction transistors in the primary side switching in an LLC circuit helps designers achieve a compact and energy-efficient power supply.
Compared to conventional planar silicon MOSFETs, the super-junction MOSFET has significantly lower conduction loss for a give die size. Additionally, architecture of the latter device allows lower gate charges and capacitances, leading to lower switching losses compared to conventional silicon transistors.
Fabricators used a multi-epitaxial process for structuring the early super-junction devices. They doped the N-region richly allowing a much lower on-resistance compared to conventional planar transistors. They adapted the P-type region bounding the N-channel to achieve the desired breakdown voltage.
The multi-epitaxial processes resulted in the N- and P-type structures being dimensionally larger than ideal and led to an associated impact on overall device size. The nature of the multi-epitaxial fabrication also restricted engineering the N-region to minimize on-resistance. Therefore, fabricators now use single-epitaxial fabrication processes such as deep trench filling to optimize the aspect ratios of N- and P-regions to minimize the on-resistance while also reducing the size of the MOSFET.
For instance, the single epitaxial fabrication process allows DTMOS IV family of Toshiba’s fourth-generation super-junction MOSFETs to achieve a 27% reduction in device pitch, while also reducing the on-resistance by 30% for each die area. Similarly, Toshiba’s DTMOS V, based on deep trench process, has further improvements at the cell structure level.
Thanks to the single-epitaxial process, the super-junction MOSFETs can deliver more stable performance when faced with temperature changes. Power converters with conventional MOSFETs are noted for reduced efficiencies at higher operating temperatures, which the super-junction MOSFETs are able to counter. For instance, super-junction MOSFETs show a12% lower on-resistance at 150°C.
Power converters using the fifth-generation super-junction DTMOS V devices can now deliver low-noise performance along with superior switching performance. A modified gate structure and patterning helps to achieve this, resulting in an increase in the reverse transfer capacitance between the gate and drain of the device.