Tag Archives: SPXO

Low-Power Circuit Timing using SPXOs

A wide range of electronic devices relies on circuit timing as a critical function. These include microcontrollers, Bluetooth, Ethernet, Wi-Fi, USB, and other interfaces. In addition, circuit timing is essential for consumer electronics, wearables, the Internet of Things (IoT), industrial control and automation, test and measuring equipment, medical devices, computing devices and peripherals, and more. Although designing crystal-controlled oscillators seems an easy process for providing system timing, there are numerous design requirements and parameters that designers must consider when matching a quartz crystal to an oscillator chip.

Among the several considerations are the negative resistance of the oscillator, its drive level, resonant mode, and the motional impedance of the crystal. When the designer is making the circuit layout, they must consider the parasitic capacitance of the PC board. They must also consider the on-chip integrated capacitance, and include a guard band around the crystal. Finally, the design must not only be compact, with a minimum number of components, and reliable. While the circuit must be capable of operating with a wide range of input voltages, consuming minimal power, it must also have a small root-mean-square jitter.

An optimal solution to the above is to use simply packaged crystal oscillators or SPXOs. Manufacturers optimize SPXOs for low RMS jitter and minimal power consumption. These devices can operate with any supply voltage ranging from 1.6 VDC to 3.6 VDC. With these continuous-voltage oscillators, designers can implement solutions requiring minimal effort while integrating them into digital systems.

In small, battery-powered, wireless devices, power consumption is always a very important consideration. That is why designers prefer to base such devices on the system on a chip or SoC processor that consumes very low power to support battery lives of several years. Moreover, device cost depends on the battery size, as the battery is easily the most expensive component in the device—minimizing the battery size is, therefore, an important factor in small wireless devices. For battery life consideration, one of the important parameters is the standby current, apart from the self-discharge current of the battery. Minimizing the current drawn by the clock oscillator is important, as this is greater than the standby current.

Designing low-power oscillators can be challenging. Designers are tempted to save energy by allowing the circuit to enter a disabled state for minimizing the standby current while starting the oscillator when needed. However, this is not an easy task as starting crystal oscillators quickly is not a simple and reliable task. Reliable start-up conditions require careful design efforts when designers attempt it across all environmental and operating conditions.

Most low-power wireless SoCs favor the Pierce oscillator configuration. The circuit has crystal and tow load capacitors. It uses an inverting amplifier that has an internal feedback resistor. With the amplifier feeding back its output to its input, the right conditions cause a negative resistance to start the oscillations going.

Quartz crystal oscillators can have jitters caused by power supply noise, improper load, improper termination conditions, the presence of integer harmonics of the signal frequency, circuit configurations, and amplifier noise. The designer must use several methods to minimize jitter.